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Veröffentlichungen

2015

Arthur Pyka, Pavel G. Zaykov, Hugues Cassé, Haluk Ozaktas, Christine Rochange, Sascha Uhrig
Case Study: Performance and WCET Analysis for Parallelised Avionic Applications with ODC²
Accepted for the 13th IEEE International Conference on Industrial Informatics (INDIN 2015), Cambridge, UK, 2015

Sascha Uhrig, Lillian Tadros and Arthur Pyka
MESI-based Cache Coherence for Hard Real-time Multicore Systems
28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015), Porto, Portugal, 2015

Arthur Pyka, Lillian Tadros, Hugues Cassé, Haluk Ozaktas, Christine Rochange, Sascha Uhrig
WCET Analysis of Parallel Benchmarks using On-Demand Coherent Cache
3rd Workshop on High-performance and Real-time Embedded Systems (HiRES 2015), Amsterdam, the Netherlands, 2015
[pdf]

T. Ungerer, C. Bradatsch, M. Frieb, F. Kluge, J. Mische, A. Stegmeier, R. Jahr, M. Gerdes, P. Zaykov, L. Matusova, Z. J. J. Li, Z. Petrov, B. Böddeker, S. Kehr, H. Regler, A. Hugl, C. Rochange, H. Ozaktas, H. Cassé, A. Bonenfant, P. Sainrat, N. Lay, D. George, I. Broster, E. Quinones, M. Panic, J. Abella, C. Hernandez, F. Cazorla, S. Uhrig, M. Rohde and A. Pyka
Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core
3nd Workshop on High-performance and Real-time Embedded Systems (HiRES 2015), Amsterdam, the Netherlands, 2015
[pdf]

 

2014

Arthur Pyka, Mathias Rohde, Sascha Uhrig
Extended Performance Analysis of the Time Predictable On-demand Coherent Data Cache for Multi- and Many-core Systems
International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS), Greece, Samos, June 14-17, 2014
[Link]

Arthur Pyka, Mathias Rohde, Sascha Uhrig
A Real-Time Capable Coherent Data Cache for Multi-cores
Concurrency and Computation: Practice & Experience, Wiley, Volume 26, Issue 6, pages 1342-1354, April 2014
[Link]

Sascha Uhrig
parMERASA - Principles of time-predictable parallelization and hardware overview

Invited talk at 2nd Workshop on Integration of Mixed-criticality Subsystems on Multi-core and Manycore Processors (MCS), Vienna, Austria, January 21, 2014

Arthur Pyka, Mathias Rohde, Pavel G. Zaykov, Sascha Uhrig
Case Study: On-Demand Coherent Cache for Avionic Applications
2nd Workshop on High Performance and Real-time Embedded Systems (HiRES), Vienna, Austria, January 20, 2014
[Link]

 

2013

Christine Rochange, Sascha Uhrig, Pascal Sainrat
Time-predictable Architectures
Wiley-ISTE, ISBN 978-1-84821-593-1, December 2013

T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P. Zaykov, Z. Petrov, B. Böddeker, S. Kehr, H. Regler, A. Hugl, C. Rochange, H. Ozaktas, H. Cassé, A. Bonenfant, P. Sainrat, I. Broster, N. Lay, D. George, E. Quiñones, M. Panic, J. Abella, F. Cazorla, S. Uhrig, M. Rohde and A. Pyka
parMERASA – Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
The 16th Euromicro Conference on Digital System Design (DSD), September 4-6, Santander, Spain
[Link]

Arthur Pyka, Mathias Rohde, Sascha Uhrig
Performance Evaluation of the Time Analysable On-Demand Coherent Cache
4th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms, July 16-18, Melbourne, Australia
[Link]

Arthur Pyka, Mathias Rohde, Joao Fernandes, Sascha Uhrig
On-Demand Coherent Cache for Parallelised Hard Real-Time Applications
Euromicro Conference on Real-Time Systems (ECRTS), Work in Progress Session, July 9-12, Paris, France
[PDF]

Marco Paolieri, Francisco J. Cazorla, Eduardo Quinones, Sascha Uhrig, Stefan Metzlaff, Jörg Mische, Theo Ungerer
A Hard Real-Time Capable Multi-Core SMT Processor
ACM Journal on Transactions on Embedded Computing Systems (TECS), Volume 12 Issue 3, March 2013, Article No. 79

Arthur Pyka, Mathias Rohde, Sascha Uhrig
A Real-Time Capable First-level Cache for Multi-cores
Workshop on High Performance and Real-time Embedded Systems (HiRES), Berlin, Germany, January 22
[PDF]

 

2012

Sascha Uhrig
Implementing a Ring-based Real-time Capable Network using a Multithreaded Java Processor
10th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2012), Copenhagen, Denmark, October 24-26

Sascha Uhrig, Ralf Jahr, Theo Ungerer
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor
IET Journal Computers & Digital Techniques, High-performance computing system architectures: Design and Performance, Volume 6, Issue 5, pages 334-341

Julian Wolf, Bernhard Fechner, Sascha Uhrig Theo Ungerer
Fine-Grained Timing and Control Flow Error Checking for Hard Real-Time Task Execution
7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), Karlsruhe, Germany, July 20-22

 

2011

Julian Wolf, Mike Gerdes, Florian Kluge, Sascha Uhrig, Jörg Mische, Stefan Metzlaff, Christine Rochange, Hugues Cassé, Pascal Sainrat, Theo Ungerer
RTOS Support for Execution of Parallelized Hard Real-Time Tasks on the MERASA Multi-Core Processor
International Journal of Computer Systems, Science & Engineering (CSSE), ISSN 0267 6192, Vol. 26, No. 6

Sascha Uhrig
Tracing Static Fields of Embedded Parallel Java Applications,
International Workshop on Program Debugging (IWPD) in conjunction with the 35th IEEE Computer oftware and Applications Conference (COMPSAC), Munich, Germany, July 18

Christian Bradatsch, Sebastian Schlingmann, Sascha Uhrig, Theo Ungerer
MANJAC - Ein Many-Core-Emulator auf Multi-FPGA-Basis,
PARS Workshop, Rüschlikon, Swiss, May 26/27

Sascha Uhrig
Moving Execution - Motion,
PARS Workshop, Rüschlikon, Swiss, May 26/27

Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Julian Wolf, Theo Ungerer, Sascha Uhrig, Zlatko Petrov
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks,
14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), Newport Beach, CA, USA, March 28-31

Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware,
Proceedings of the Architecture of Computing Systems Conference (ARCS 2011), Como, Italy, February 22-25

Ralf Jahr, Basher Shehan, Sascha Uhrig, Theo Ungerer
Optimized Replacement in the Configuration Layers of the Grid Alu Processor,
Proceedings of the 2nd International Workshop on New Frontiers in High-Performance and Hardware-aware Computing (HipHac´11), San Antonio, TX, USA, February 13

 

 

2010

Please see my former homepage at University of Augsburg.